A typical NAND flash memory device 10 is shown in FIG. 1. The device 10 is comprised of a large number of flash memory cells, collectively indicated by reference numeral 14. The array of flash memory cells 14 is typically divided into a number of blocks, one of which is shown in FIG. 1. Each block includes a number of rows, which, in the example shown in FIG. 1, includes 32 rows, and a number of columns, which, in the example shown in FIG. 1, includes 1600 columns. The cells 14 in the same row have their control gates coupled to a common word line 20, each of which receives a respective word line signal WL0-WL31 from a respective NMOS string driver transistor 22. The gates of all of the string drive transistors 22 are coupled to a common gate driver 23, which applies either ground or an elevated string driver voltage “Vstrdrv” to the gates of the transistors 22. The drains of the string driver transistors 22, which are normally part of a row decoder (not shown), are coupled to respective global word lines (“GWL”) 24. The global word lines 24 are connected to a global word line driver 26, which serves as a voltage selector circuit.
As further shown in FIG. 1, the global word line driver 26 includes a row decoder 28 coupled to receive voltages from an analog voltage supply circuit 30. The voltage generated by the analog voltage supply circuit 30 includes a programming voltage Vpgm, a pass voltage Vpass, and a bias voltage Vbias1. (FIG. 1 also shows the analog voltage supply circuit 30 as generating a second bias voltage Vbias2, but this bias voltage is not used in prior art devices and can be ignored for now). The analog voltage supply circuit 30 is controlled by a first set of control signals. The row decoder 28 also receives a row address RA. The row decoder 28 includes a respective voltage selector 32 for each of the global word lines 24. The voltage selectors 32 couple the voltages from the voltage supply circuit 30 to selected ones of the string driver transistors 22 responsive to a second set of control signals. The first set of control signals that are received by the analog voltage supply circuit 30 and the second set of signals that are received by the voltage selectors 32 are generated by a micro controller 34, although other control devices could be used.
In operation, the micro controller 34 causes each of the voltage selectors 32 to apply a voltage to its respective global word line 24 depending on the operation being performed and the row address, which is indicative of the row of memory cells 14 on which the operation is being performed. More specifically, each of the selectors 32 can apply either a programming voltage Vpgm, a pass voltage Vpass, or a bias voltage Vbias1 to its respective global word line 24, which is then coupled by the respective string driver transistor 22 to the respective word line 20.
As also shown in FIG. 1, the cells 14 in the same column have their sources and drains connected to each other in series. Thus all of the memory cells 14 in the same column of each block are typically connected in series with each other. The drain of the upper flash memory cell 14 in the block is coupled to a bit line 40 through a first select gate transistor 42. The conductive state of the transistors 42 in each block are controlled by a select gate drain (“sgd”) signal, which is generated by an NMOS string driver transistor 44. Each of the bit lines 40 output a respective bit line signal BL0-BLN indicative of the data bit stored in the respective column of the array of memory cells 14. The bit lines 40 extend through multiple blocks to respective sense amplifiers (not shown). The source of the lower flash memory cell 14 in the block is coupled to a source line 46 through a second select gate transistor 48. The conductive state of the transistors 48 in each block are controlled by a select gate source (“sgs”) signal, which is also generated by an NMOS string driver transistor 50. The source line 46 receives a signal SRC having various magnitudes depending upon whether the memory cells 14 are being programmed, read or erased.
As mentioned above, the voltage that the voltage selectors 32 apply to the respective word lines 20 depends on which row of memory cells 14 are “active,” i.e., which row is being programmed, erased or read. The word line 20 for the active row is referred to as a “local win” word line, the word lines 20 adjacent the selected word line are referred to as the “local wln+1” and “local wln−1,” the word lines adjacent those word lines are referred to as the “local wln+2” and “local wln−2,” and the remaining word lines are referred to as “unselected” word lines.
The manner in which the string driver transistors 22 are driven is shown in FIG. 2. At time t0, the gate driver 23 (FIG. 1) applies the Vstrdry voltage to the gates of the string driver transistors 22. Shortly thereafter at time t1, voltage selectors 32 apply a bias voltage Vbias1 to the drains of the string driver transistors 22 for the word lines WLn±1 and WLn±2 adjacent the active row. At time t2, the respective voltage selectors 32 apply the Vpass voltage to the drains of all of the string driver transistors 22 for all of the unselected word lines. Finally, at time t3, the respective voltage selector 32 applies the Vpgm voltage to the drain of the string driver transistors 22 for the word line WLn of the active row.
As also shown in FIG. 2, even though the programming voltage Vpgm may be substantially greater than the Vstrdry voltage, the word line WLn of the active row is not driven to the level of the Vstrdry voltage. Instead, the word line WLn is driven to the Vstrdry voltage less the threshold voltage VT of the string driver transistor 22 for the active row. As a result, it may not be possible to drive the voltage of the WLn of the active row to a level that is sufficient to provide optimal programming efficiency. More specifically, as shown in FIG. 3, the micro controller 34 normally causes the analog voltage supply circuit 30 to generate the voltages from the circuit 30 in the form of respective series of pulses that may sequentially increase in amplitude. After each set of pulses, the memory cells 14 in the row being programmed are normally read to determine if the cells have been programmed to target charge levels. If so, further programming is terminated. This iterative “program and then verify” is particularly important for multi-level memory cells in which the memory cells 14 are programmed to one of four or more levels.
The program voltage Vpgm is normally generated by the analog voltage supply circuit 30 as successive pulses of incrementally increasing magnitude, one of which is shown in FIG. 2. Unfortunately, the string driver transistors 22 are sometimes unable to pass these increases in the magnitude of Vpgm pulses beyond the magnitude of the programming voltage Vpgm less the threshold voltage VT of the string driver transistor 22. For example, as further shown in FIG. 3, the pulses of Vpgm sequentially increase as follows: 16v, 16.5v, 17v, 17.5v, 18v, 18.5v, 19v, 19.5v. In this example, it is assumed the Vstrdry voltage is 20 volts, and the threshold voltage VT of the string driver transistor 22 is 2 volts. Therefore, the string driver transistor 22 cannot apply more than 18 volts to the word line WLn regardless of the level of Vpgm. As a result, once the pulses of Vpgm reaches 18 volts, the voltage on the word line WLn remains at 18 volts even though the pulses of Vpgm continue to increase, as shown by the dotted lines in FIG. 3. The string driver transistors 22 are therefore unable to apply the full magnitude of the Vpgm voltage to the word line WLn of the active row, thereby limiting programming efficiency.
The problem of the string driver transistors 22 being unable to apply the full magnitude of the programming voltage Vpgm to the selected word line 20 can also exist with the string driver transistors 44, 50 for the select gate transistors 42, 48. Further, although the problem of string driver transistors being unable to apply the full magnitude of voltages applied to their drains has been explained in the context of a flash memory device, it will be understood that the problem can also exist in other types of non-volatile memory devices.
There is therefore a need for a circuit and method that can allow string driver transistors to apply voltages to word lines as well as possibly select gate and other lines with reduced loss in voltage across the string driver transistors.